(Not Applicable)
1. Field of the Invention
The present invention is directed generally to a semiconductor raised source-drain structure and, more particularly, to a semiconductor raised source-drain structure with gate side gaps and pocket junctions.
2. Description of the Background
Raised source and drains have been demonstrated in submicron semiconductor devices. In contrast to conventional source and drains, raised source and drains are vertical structures formed on top of the substrate instead of implanted structures in the substrate surface. Thin film structures are typically inserted between the sidewalls of the gate and the top regions of the raised source and drains to isolate the gate from the source and drains. Such an isolation arrangement, however, can cause excessive capacitive loading from gate to source and drain.
Devices incorporating raised source and drains typically include implanted nxe2x88x92 regions under the source and drain regions to create conductive channels between the gate and the source and drains. Such channels do not have good drive and punchthrough capabilities. Also, it is difficult to implant the conductive channels after the polysilicon pattern defining the source and drain structures.
Thus, there is a need for a semiconductor device with raised source and drains that has improved series resistance, good IDS current drive, improved punchthrough leakage, and reduced sidewall capacitance that can be fabricated using standard fabrication techniques.
The present invention is directed to a system comprising a memory device that includes at least one semiconductor structure wherein the semiconductor structure includes raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping layer in communication with at least a portion of the gate and the drain, a first portion of a gate oxide region in communication with at least a portion of the gate and the source, a second portion of a gate oxide region in communication with at least a portion of the gate and the drain. The source, the gate, the first capping layer, and the first portion of a gate oxide region define a first gap. The drain, the gate, the second capping layer, and the second portion of a gate oxide region define a second gap. The semiconductor structure also includes a first junction area located beneath the first gap, the gate and the source and a second junction area located beneath the second gap, the gate and the drain. The system also includes a processor and a bus connecting the processor and the memory device.
The present invention represents a substantial advance over prior raised source and drain structures. The present invention has the advantage that it improves the sidewall decoupling of the raised source-drain to the polysilicon gate. In one embodiment, the present invention also has the advantage that it connects the source and drain to the pocket junction next to the gate edge with a high dose implant for reduced series resistance. In another embodiment, the present invention has the further advantage that the full CMOS process flow is reduced compared to typical raised source-drain CMOS process flows by making raised source-drain structures of n+ and p+ polysilicon with respective pocket junctions by implantation. The present invention also has the advantage that conductive source and drain structures can be placed closer to the polysilicion gate, thereby reducing the size of the structure. The present invention also has the advantage that implanted areas between the gate and source and drain structures can be fabricated using conventional semiconductor processing techniques. The present invention has the further advantage that current may move from the implanted areas to the raised source and drain structures with minimal resistance. Those and other advantages and benefits of the present invention will become apparent from the description of the preferred embodiments hereinbelow.